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| ds05-20846-4e fujitsu semiconductor data sheet flash memory cmos 16m (2m 8/1m 16) bit mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n features ? single 3.0 v read, program and erase minimizes system level power requirements ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts 48-pin tsop (i) (package suffix: pftn-normal bend type, pftr-reversed bend type) 46-pin son (package suffix: pn) 48-pin csop (package suffix: pcv) 48-ball fbga (package suffix: pbt) ? minimum 100,000 program/erase cycles ? high performance 80 ns maximum access time ? sector erase architecture one 8k word, two 4k words, one 16k word, and thirty-one 32k words sectors in word mode one 16k byte, two 8k bytes, one 32k byte, and thirty-one 64k bytes sectors in byte mode any combination of sectors can be concurrently erased. also supports full chip erase ? boot code sector architecture t = top sector b = bottom sector ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm algorithms automatically programs and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switches themselves to low power mode ?low v cc write inhibit 2.5 v (continued) embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
2 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 (continued) ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector protection hardware method disables any combination of sectors from program or erase operations ? sector protection set function by extended sector protect command ? temporary sector unprotection temporary sector unprotection via the reset pin ? in accordance with cfi (c ommon f lash memory i nterface) n pac k ag e 48-pin plastic tsop (i) 46-pin plastic son (fpt-48p-m20) (lcc-46p-m02) (fpt-48p-m19) marking side marking side 48-pin plastic fbga (bga-48p-m03) (bga-48p-m13) 48-pin plastic csop (lcc-48p-m03) 3 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n general description the mbm29lv160t/b is a 16m-bit, 3.0 v-only flash memory organized as 2m bytes of 8 bits each or 1m words of 16 bits each. the mbm29lv160t/b is offered in a 48-pin tsop (i), 46-pin son, 48-pin csop and 48-ball fbga packages. the device is designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the standard mbm29lv160t/b offers access times of 80 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29lv160t/b is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29lv160t/b is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margins. any individual sector is typically erased and verified in 1.0 second. (if already preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29lv160t/b is erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. the mbm29lv160t/b also has a hardware reset pin. when this pin is driven low, execution of any embedded program algorithm or embedded erase algorithm is terminated. the internal state machine is then reset to the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. these locations need re-writing after the reset. resetting the device enables the systems microprocessor to read the boot-up firmware from the flash memory. fujitsus flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29lv160t/b memory electrically erases all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection. 4 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n flexible sector-erase architecture ? one 8k word, two 4k words, one 16k word, and thirty-one 32k words sectors in word mode. ? one 16k byte, two 8k bytes, one 32k byte, and thirty-one 64k bytes sectors in byte mode. ? individual-sector, multiple-sector, or bulk-erase capability. ? individual or multiple-sector protection is user definable. mbm29lv160t top boot sector architecture sector sector size ( 8) address range ( 16) address range sa0 64 kbytes or 32 kwords 00000h to 0ffffh 00000h to 07fffh sa1 64 kbytes or 32 kwords 10000h to 1ffffh 08000h to 0ffffh sa2 64 kbytes or 32 kwords 20000h to 2ffffh 10000h to 17fffh sa3 64 kbytes or 32 kwords 30000h to 3ffffh 18000h to 1ffffh sa4 64 kbytes or 32 kwords 40000h to 4ffffh 20000h to 27fffh sa5 64 kbytes or 32 kwords 50000h to 5ffffh 28000h to 2ffffh sa6 64 kbytes or 32 kwords 60000h to 6ffffh 30000h to 37fffh sa7 64 kbytes or 32 kwords 70000h to 7ffffh 38000h to 3ffffh sa8 64 kbytes or 32 kwords 80000h to 8ffffh 40000h to 47fffh sa9 64 kbytes or 32 kwords 90000h to 9ffffh 48000h to 4ffffh sa10 64 kbytes or 32 kwords a0000h to affffh 50000h to 57fffh sa11 64 kbytes or 32 kwords b0000h to bffffh 58000h to 5ffffh sa12 64 kbytes or 32 kwords c0000h to cffffh 60000h to 67fffh sa13 64 kbytes or 32 kwords d0000h to dffffh 68000h to 6ffffh sa14 64 kbytes or 32 kwords e0000h to effffh 70000h to 77fffh sa15 64 kbytes or 32 kwords f0000h to fffffh 78000h to 7ffffh sa16 64 kbytes or 32 kwords 100000h to 10ffffh 80000h to 87fffh sa17 64 kbytes or 32 kwords 110000h to 11ffffh 88000h to 8ffffh sa18 64 kbytes or 32 kwords 120000h to 12ffffh 90000h to 97fffh sa19 64 kbytes or 32 kwords 130000h to 13ffffh 98000h to 9ffffh sa20 64 kbytes or 32 kwords 140000h to 14ffffh a0000h to a7fffh sa21 64 kbytes or 32 kwords 150000h to 15ffffh a8000h to affffh sa22 64 kbytes or 32 kwords 160000h to 16ffffh b0000h to b7fffh sa23 64 kbytes or 32 kwords 170000h to 17ffffh b8000h to bffffh sa24 64 kbytes or 32 kwords 180000h to 18ffffh c0000h to c7fffh sa25 64 kbytes or 32 kwords 190000h to 19ffffh c8000h to cffffh sa26 64 kbytes or 32 kwords 1a0000h to 1affffh d0000h to d7fffh sa27 64 kbytes or 32 kwords 1b0000h to 1bffffh d8000h to dffffh sa28 64 kbytes or 32 kwords 1c0000h to 1cffffh e0000h to e7fffh sa29 64 kbytes or 32 kwords 1d0000h to 1dffffh e8000h to effffh sa30 64 kbytes or 32 kwords 1e0000h to 1effffh f0000h to f7fffh sa31 32 kbytes or 16 kwords 1f0000h to 1f7fffh f8000h to fbfffh sa32 8 kbytes or 4 kwords 1f8000h to 1f9fffh fc000h to fcfffh sa33 8 kbytes or 4 kwords 1fa000h to 1fbfffh fd000h to fdfffh sa34 16 kbytes or 8 kwords 1fc000h to 1fffffh fe000h to fffffh 5 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 mbm29lv160b bottom boot sector architecture sector sector size ( 8) address range ( 16) address range sa0 16 kbytes or 8 kwords 00000h to 03fffh 00000h to 01fffh sa1 8 kbytes or 4 kwords 04000h to 05fffh 02000h to 02fffh sa2 8 kbytes or 4 kwords 06000h to 07fffh 03000h to 03fffh sa3 32 kbytes or 16 kwords 08000h to 0ffffh 04000h to 07fffh sa4 64 kbytes or 32 kwords 10000h to 1ffffh 08000h to 0ffffh sa5 64 kbytes or 32 kwords 20000h to 2ffffh 10000h to 17fffh sa6 64 kbytes or 32 kwords 30000h to 3ffffh 18000h to 1ffffh sa7 64 kbytes or 32 kwords 40000h to 4ffffh 20000h to 27fffh sa8 64 kbytes or 32 kwords 50000h to 5ffffh 28000h to 2ffffh sa9 64 kbytes or 32 kwords 60000h to 6ffffh 30000h to 37fffh sa10 64 kbytes or 32 kwords 70000h to 7ffffh 38000h to 3ffffh sa11 64 kbytes or 32 kwords 80000h to 8ffffh 40000h to 47fffh sa12 64 kbytes or 32 kwords 90000h to 9ffffh 48000h to 4ffffh sa13 64 kbytes or 32 kwords a0000h to affffh 50000h to 57fffh sa14 64 kbytes or 32 kwords b0000h to bffffh 58000h to 5ffffh sa15 64 kbytes or 32 kwords c0000h to cffffh 60000h to 67fffh sa16 64 kbytes or 32 kwords d0000h to dffffh 68000h to 6ffffh sa17 64 kbytes or 32 kwords e0000h to effffh 70000h to 77fffh sa18 64 kbytes or 32 kwords f0000h to fffffh 78000h to 7ffffh sa19 64 kbytes or 32 kwords 100000h to 10ffffh 80000h to 87fffh sa20 64 kbytes or 32 kwords 110000h to 11ffffh 88000h to 8ffffh sa21 64 kbytes or 32 kwords 120000h to 12ffffh 90000h to 97fffh sa22 64 kbytes or 32 kwords 130000h to 13ffffh 98000h to 9ffffh sa23 64 kbytes or 32 kwords 140000h to 14ffffh a0000h to a7fffh sa24 64 kbytes or 32 kwords 150000h to 15ffffh a8000h to affffh sa25 64 kbytes or 32 kwords 160000h to 16ffffh b0000h to b7fffh sa26 64 kbytes or 32 kwords 170000h to 17ffffh b8000h to bffffh sa27 64 kbytes or 32 kwords 180000h to 18ffffh c0000h to c7fffh sa28 64 kbytes or 32 kwords 190000h to 19ffffh c8000h to cffffh sa29 64 kbytes or 32 kwords 1a0000h to 1affffh d0000h to d7fffh sa30 64 kbytes or 32 kwords 1b0000h to 1bffffh d8000h to dffffh sa31 64 kbytes or 32 kwords 1c0000h to 1cffffh e0000h to e7fffh sa32 64 kbytes or 32 kwords 1d0000h to 1dffffh e8000h to effffh sa33 64 kbytes or 32 kwords 1e0000h to 1effffh f0000h to f7fffh sa34 64 kbytes or 32 kwords 1f0000h to 1fffffh f8000h to fffffh 6 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n product line up n block diagram part no. mbm29lv160t/160b ordering part no. v cc = 3.3 v -80 v cc = 3.0 v -90-12 max. address access time (ns) 80 90 120 max. ce access time (ns) 80 90 120 max. oe access time (ns) 30 35 50 +0.3 v C0.3 v +0.6 v C0.3 v v ss v cc we ce a 0 to a 19 oe erase voltage generator dq 0 to dq 15 state control command register program voltage generator low v cc detector address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch input/output buffers stb stb a -1 byte reset ry/by buffer ry/by timer for program/erase 7 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n connection diagrams (continued) standard pinout tsop(i) (marking side) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 n.c. we reset n.c. n.c. ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 fpt-48p-m19 reverse pinout (marking side) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry/by n.c. n.c. reset we n.c. a 19 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a -1 v ss byte a 16 fpt-48p-m20 (top view) (marking side) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 lcc- son-46 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 a 13 a 14 a 15 a 12 a 11 a 10 a 9 a 8 a 19 we reset v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 a 16 byte v ss dq 15 /a -1 a 3 a 2 a 1 a 4 a 5 a 6 a 7 a 17 a 18 ry/by n.c. dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 a 0 ce v ss oe 46p-m02 8 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 (continued) (top view) csop-48 lcc-48p-m03 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry / by n.c. n.c. reset we n.c. a 19 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 / a -1 v ss byte a 16 a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 marking side (top view) fbga (bga-48p-m03) (bga-48p-m13) a1 a 3 a2 a 7 a3 ry/by a4 we a5 a 9 a6 a 13 b1 a 4 b2 a 17 b3 n.c. b4 reset b5 a 8 b6 a 12 c1 a 2 c2 a 6 c3 a 18 c4 n.c. c5 a 10 c6 a 14 d1 a 1 d2 a 5 d3 n.c. d4 a 19 d5 a 11 d6 a 15 e1 a 0 e2 dq 0 e3 dq 2 e4 dq 5 e5 dq 7 e6 a 16 f1 ce f2 dq 8 f3 dq 10 f4 dq 12 f5 dq 14 f6 byte g1 oe g2 dq 9 g3 dq 11 g4 v cc g5 dq 13 g6 dq 15 /a -1 h1 v ss h2 dq 1 h3 dq 3 h4 dq 4 h5 dq 6 h6 v ss 9 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n logic symbol 20 a 0 to a 19 we ry/by oe ce a -1 dq 0 to dq 15 16 or 8 reset byte table 1 mbm29lv160t/b pin configuration pin function address inputs data inputs/outputs chip enable output enable write enable pin not connected internally ready/busy output device ground device power supply hardware reset pin/ temporary sector unprotection a -1 , a 0 to a 19 dq 0 to dq 15 ce oe we reset n.c. ry/by selects 8-bit or 16-bit mode byte v ss v cc 10 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 legend: l = v il , h = v ih , x = v il or v ih . = pulse input. see dc characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. see table 7. 2. refer to the section on sector protection. 3. we can be v il if oe is v il , oe at v ih initiates the write operations. 4. v cc = 3.3 v 10% 5. it is also used for the extended sector protection. table 2 mbm29lv160t/b user bus operation (byte = v ih ) operation ce oe we a 0 a 1 a 6 a 9 dq 0 to dq 15 reset auto-select manufacture code (1) l l h l l l v id code h auto-select device code (1) l l h h l l v id code h read (3) l l h a 0 a 1 a 6 a 9 d out h standby hxxxxxxhigh-z h output disable lhhxxxxhigh-z h write (program/erase) l h l a 0 a 1 a 6 a 9 d in h enable sector protection (2), (4) l v id lhlv id xh verify sector protection (2), (4) l l h l h l v id code h temporary sector unprotection (5) x x x x x x x x v id reset (hardware)/standby xxxxxxxhigh-z l table 3 mbm29lv160t/b user bus operation (byte = v il ) operation ce oe we dq 15 /a -1 a 0 a 1 a 6 a 9 dq 0 to dq 7 reset auto-select manufacture code (1) l l h l l l l v id code h auto-select device code (1) l l h l h l l v id code h read (3) l l h a -1 a 0 a 1 a 6 a 9 d out h standby h x x x x x x x high-z h output disable l h h x x x x x high-z h write (program/erase) l h l a -1 a 0 a 1 a 6 a 9 d in h enable sector protection (2), (4) l v id llhlv id xh verify sector protection (2), (4) l l h l l h l v id code h temporary sector unprotection (5) x x x x x x x x x v id reset (hardware)/standby x x x x x x x x high-z l 11 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm29lv160 t -80 pftn device number/description mbm29lv160 16 mega-bit (2m 8-bit or 1m 16-bit) cmos flash memory 3.0 v-only read, write, and erase pa c k a g e t y p e pftn = 48-pin thin small outline package (tsop) standard pinout pftr = 48-pin thin small outline package (tsop) reverse pinout pn =46-pin small outline nonleaded package (son) pcv = 48-pin c- leaded small outline package (csop) pbt = 48-pin fine pitch ball grid array package (fbga:bga-48p-m03) pbt- sf2= 48-pin fine pitch ball grid array package (fbga:bga-48p-m13) speed option see product selector guide boot code sector architecture t = top sector b = bottom sector 12 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n functional description read mode the mbm29lv160t/b has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc - t oe time.) see figure 5.1 for timing specifications. standby mode there are two ways to implement the standby mode on the mbm29lv160t/b devices. one is by using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with the reset input held at v ss 0.3 v (ce = h or l). under this condition the current consumed is less than 5 m a max. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode, the outputs are in the high-impedance state, independent of the oe input. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29lv160t/b data. this mode can be used effectively with an application requesting low power consumption such as handy terminals. to activate this mode, mbm29lv160t/b automatically switches itself to low power mode when addresses remain stable for 150 ns. it is not necessary to control ce , we , and oe in this mode. during such mode, the current consumed is typically 1 m a (cmos level). standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. output disable if the oe input is at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high-impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. the intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. the autoselect command may also be used to check the status of write-protected sectors. (see tables 4.1 and 4.2.) this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , and a 6 (a -1 ). (see table 2 or table 3.) 13 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 the manufacturer and device codes may also be read via the command register, for instances when the mbm29lv160t/b is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 7, command definitions. byte 0 (a 0 = v il ) represents the manufactures code and byte 1 (a 0 = v ih ) represents the device identifier code. for the mbm29lv160t/b these two bytes are given in the table 4.2. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see tables 2 or 3.) for device indentification in word mode (byte = v ih ), dq 9 and dq 13 are equal to 1 and dq 8 , dq 10 to dq 12 , dq 14 , and dq 15 are equal to 0. if byte = v il (for byte mode), the device code is c4h (for top boot block) or 49h (for bottom boot block). if byte = v ih (for word mode), the device code is 22c4h (for top boot block) or 2249h (for bottom boot block). in order to determine which sectors are write protected, a 1 must be at v ih while running through the sector addresses; if the selected sector is protected, a logical 1 will be output on dq 0 (dq 0 =1). *1: a -1 is for byte mode. *2: outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. (b): byte mode (w): word mode table 4.1 mbm29lv160t/b sector protection verify autoselect code type a 12 to a 18 a 6 a 1 a 0 a -1 * 1 code (hex) manufactures code x v il v il v il v il 04h device code mbm29lv160t byte xv il v il v ih v il c4h word x 22c4h mbm29lv160b byte xv il v il v ih v il 49h word x 2249h sector protection sector addresses v il v ih v il v il 01h* 2 table 4.2 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code 04h a -1 /00000000 00000100 device code mbm29lv160t (b) c4h a -1 hi-zhi-zhi-zhi-zhi-zhi-zhi-z11000100 (w) 22c4h 00100010 11000100 mbm29lv160b (b) 49h a -1 hi-zhi-zhi-zhi-zhi-zhi-zhi-z01001001 (w) 2249h 00100010 01001001 sector protection 01h a -1 /00000000 00000001 14 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 table 5 sector address tables (mbm29lv160t) sector address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 ( 8) address range ( 16) address range sa0 00000xxx0 0000h to 0ffffh 00000h to 07fffh sa1 00001xxx1 0000h to 1ffffh 08000h to 0ffffh sa2 00010xxx2 0000h to 2ffffh 10000h to 17fffh sa3 00011xxx3 0000h to 3ffffh 18000h to 1ffffh sa4 00100xxx4 0000h to 4ffffh 20000h to 27fffh sa5 00101xxx5 0000h to 5ffffh 28000h to 2ffffh sa6 00110xxx6 0000h to 6ffffh 30000h to 37fffh sa7 00111xxx7 0000h to 7ffffh 38000h to 3ffffh sa8 01000xxx8 0000h to 8ffffh 40000h to 47fffh sa9 01001xxx9 0000h to 9ffffh 48000h to 4ffffh sa10 01010xxxa 0000h to affffh 50000h to 57fffh sa11 01011xxxb 0000h to bffffh 58000h to 5ffffh sa12 01100xxxc 0000h to cffffh 60000h to 67fffh sa13 01101xxxd 0000h to dffffh 68000h to 6ffffh sa14 01110xxxe 0000h to effffh 70000h to 77fffh sa15 01111xxxf 0000h to fffffh 78000h to 7ffffh sa16 10000xxx10 0000h to 10ffffh 80000h to 87fffh sa17 10001xxx11 0000h to 11ffffh 88000h to 8ffffh sa18 10010xxx12 0000h to 12ffffh 90000h to 97fffh sa19 10011xxx13 0000h to 13ffffh 98000h to 9ffffh sa20 10100xxx14 0000h to 14ffffh a0000h to a7fffh sa21 10101xxx15 0000h to 15ffffh a8000h to affffh sa22 10110xxx16 0000h to 16ffffh b0000h to b7fffh sa23 10111xxx17 0000h to 17ffffh b8000h to bffffh sa24 11000xxx18 0000h to 18ffffh c0000h to c7fffh sa25 11001xxx19 0000h to 19ffffh c8000h to cffffh sa26 11010xxx1a 0000h to 1affffh d0000h to d7fffh sa27 11011xxx1b 0000h to 1bffffh d8000h to dffffh sa28 11100xxx1c 0000h to 1cffffh e0000h to e7fffh sa29 11101xxx1d 0000h to 1dffffh e8000h to effffh sa30 11110xxx1e 0000h to 1effffh f0000h to f7fffh sa31 111110xx1f0000h to 1f7fffhf 8000h to fbfffh sa32 111111001f8000h to 1f9fffhfc000h to fcfffh sa33 111111011fa000h to 1fbfffhfd000h to fdfffh sa34 1111111x1fc 000h to 1fffffh fe000h to fefffh 15 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 table 6 sector address tables (mbm29lv160b) sector address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 ( 8) address range ( 16) address range sa0 0000000x 00000h to 03fffh 00000h to 01fffh sa1 00000010 04000h to 05fffh 02000h to 02fffh sa2 00000011 06000h to 07fffh 03000h to 03fffh sa3 0000010x0 8000h to 0ffffh 04000h to 07fffh sa4 00001xxx1 0000h to 1ffffh 08000h to 0ffffh sa5 00010xxx2 0000h to 2ffffh 10000h to 17fffh sa6 00011xxx3 0000h to 3ffffh 18000h to 1ffffh sa7 00100xxx4 0000h to 4ffffh 20000h to 27fffh sa8 00101xxx5 0000h to 5ffffh 28000h to 2ffffh sa9 00110xxx6 0000h to 6ffffh 30000h to 37fffh sa10 00111xxx7 0000h to 7ffffh 38000h to 3ffffh sa11 01000xxx8 0000h to 8ffffh 40000h to 47fffh sa12 01001xxx9 0000h to 9ffffh 48000h to 4ffffh sa13 01010xxxa 0000h to affffh 50000h to 57fffh sa14 01011xxxb 0000h to bffffh 58000h to 5ffffh sa15 01100xxxc 0000h to cffffh 60000h to 67fffh sa16 01101xxxd 0000h to dffffh 68000h to 6ffffh sa17 01110xxxe 0000h to effffh 70000h to 77fffh sa18 01111xxxf 0000h to fffffh 78000h to 7ffffh sa19 10000xxx10 0000h to 1fffffh 80000h to 87fffh sa20 10001xxx11 0000h to 11ffffh 88000h to 8ffffh sa21 10010xxx12 0000h to 12ffffh 90000h to 97fffh sa22 10011xxx13 0000h to 13ffffh 98000h to 9ffffh sa23 10100xxx14 0000h to 14ffffh a0000h to a7fffh sa24 10101xxx15 0000h to 15ffffh a8000h to 8ffffh sa25 10110xxx16 0000h to 16ffffh b0000h to b7fffh sa26 10111xxx17 0000h to 17ffffh b8000h to bffffh sa27 11000xxx18 0000h to 18ffffh c0000h to c7fffh sa28 11001xxx19 0000h to 19ffffh c8000h to cffffh sa29 11010xxx1a 0000h to 1affffh d0000h to d7fffh sa30 11011xxx1b 0000h to 1bffffh d8000h to dffffh sa31 11100xxx1c 0000h to 1cffffh e0000h to e7fffh sa32 11101xxx1d 0000h to 1dffffh e8000h to effffh sa33 11110xxx1e 0000h to 1effffh f0000h to f7fffh sa34 11111xxx1f 0000h to 1fffffh f8000h to fffffh 16 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 write device erasure and programming are accomplished via the command register. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of ce or we , whichever occurs later, while data is latched on the rising edge of ce or we pulse, whichever occurs first. standard microprocessor write timings are used. see figures 6 to 8. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the mbm29lv160t/b features hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 34). the sector protection feature is enabled using programming equipment at the users site. the device is shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , ce = v il , a 0 = a 6 = v il , a 1 = v ih . the sector addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. tables 5 and 6 define the sector address for each of the thirty five (35) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see figures 16 and 24 for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. otherwise the device will read 00h for an unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to v il in byte mode. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) represents the sector address will produce a logical 1 at dq 0 for a protected sector. see tables 4.1 and 4.2 for autoselect codes. temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the mbm29lv160t/b devices in order to change data. the sector unprotection mode is activated by setting the reset pin to high voltage (12 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously protected sectors will be protected again. (see figures 18 and 25.) 17 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 notes: 1. address bits a 11 to a 19 = x = h or l for all address commands except or program address (pa) and sector address (sa). 2. bus operations are defined in tables 2 and 3. 3. ra =address of the memory location to be read. pa =address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa =address of the sector to be erased. the combination of a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. 4. rd =data read from location ra during read operation. pd =data to be programmed at location pa. data is latched on the rising edge of we . 5. the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 0 to a 10 byte mode: aaah or 555h to addresses a -1 to a 10 6. both read/reset commands are functionally equivalent, resetting the device to the read mode. table 7 mbm29lv160t/b standard command definitions command sequence (notes 1, 2, 3, 5) bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data read/reset (note 6) word /byte 1xxxhf0h read/reset (note 6) word 3 555h aah 2aah 55h 555h f0h ra rd byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h 555h 90h byte aaah 555h aaah byte/word program (notes 3, 4) word 4 555h aah 2aah 55h 555h a0h pa pd byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aah sector erase (note 3) word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h sector erase suspend word /byte 1xxxhb0h sector erase resume word /byte 1xxxh30h 18 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 spa : sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd : sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. *1 . this command is valid while fast mode. *2 . addresses from system set to a 0 to a 6 . the other addresses are dont care. *3 . this command is valid while v id = reset . *4 . the data" ooh" is also acceptable. command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in an improper sequence will reset the device to the read mode. table 7 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 0 to dq 7 and dq 8 to dq 15 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read mode, the read/reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory contents occurs during the power transition. refer to the ac read characteristics and waveforms for specific timing parameters. (see figure 5.1.) autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufactures and device codes must be accessible while the device resides in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. table 8 mbm29lv160t/b extended command definitions command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read cycle addr data addr data addr data addr data set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program *1 word 2 xxxh a0h pa pd byte xxxh reset from fast mode *1 word 2 xxxh 90h xxxh f0h *4 byte xxxh xxxh query command *2 word 2 55h 98h byte aah extended sector protect *3 word 4 xxxh 60h spa 60h spa 40h spa sd byte 19 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following the last command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h for 16 (xx02h for 8) retrieves the device code (mbm29lv160t = c4h and mbm29lv160b = 49h for 8 mode; mbm29lv160t = 22c4h and mbm29lv160b = 2249h for 16 mode). (see tables 4.1 and 4.2.) all manufactures and device codes will exhibit odd parity with dq 7 defined as the parity bit. the sector state (protection or unprotection) will be indicated by address xx02h for 16 (xx04h for 8). scanning the sector addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should be perform margin mode verification on the protected sector. (see tables 2 and 3.) to terminate the operation, it is necessary to write the read/reset command sequence into the register and, also to write the autoselect command during the operation, by executing it after writing the read/reset command sequence. word/byte programming the device is programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of the last ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. (see figures 6 and 7.) the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the device return to the read mode and addresses are no longer latched. (see table 8, hardware sequence flags.) therefore, the device requires that a valid address be supplied by the system at this time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occures during the programming operation, it is impossible to guarantee whether the data being written is correct or not. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. figure 20 illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six-bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. (preprogram function.) the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read mode. (see figure 8.) figure 21 illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase 20 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 sector erase is a six-bus cycle operation. there are two unlock write cycles, followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data = 30h) is latched on the rising edge of we . after a time-out of 50 m s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing six-bus cycle operations on table 7. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 m s otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 50 m s time-out window the timer is reset. monitor dq 3 to determine if the sector erase timer window is still open. (see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. resetting the device once excution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 34). sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. (see figure 8.) the automatic sector erase begins after the 50 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section) at which time the device returns to the read mode. data polling must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector program time (preprogramming) + sector erase time] number of sector erase. figure 21 illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or program to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume commands. when the erase suspend command is written during the sector erase operation, the device will take a maximum of 20 m s to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/ by output pin and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must 21 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 , or the toggle bit (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. extended command (1) fast mode mbm29lv160t/b has fast mode function. this mode dispenses with the initial two unlock cycles required in the standard program command sequence writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. (refer to the figure 26 extended algorithm.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to the figure 26 extended algorithm.) (3) cfi (common flash memory interface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward-and backward- compatible software support for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. following the command write, a read cycle from specific address retrives device information. please note that output data of upper byte (dq 8 to dq 15 ) is 0 in word mode (16 bit) read. refer to the cfi code table. to terminate operation, it is necessary to write the read/reset command sequence into the register. (4) extended sector protect in addition to normal sector protection, the mbm29lv160t/b has extended sector protection as extended function. this function enable to protect sector by forcing v id on reset pin and write a commnad sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector protection in this mode. the extended sector protect requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector to be protected (recommend to set v il for the other addresses pins), and write extended sector protect command (60h). a sector is typically protected in 150 m s. to verify programming of the protection circuitry, the sector addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector protect command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . 22 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 write operation status notes: 1. performing successive read operations from any address will cause dq 6 to toggle. 2. reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. 3. dq 0 and dq 1 are reserve pins for future use. 4. dq 4 is fujitsu internal use only. dq 7 data polling the mbm29lv160t/b device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in figure 22. for chip erase and sector erase, data polling is valid after the rising edge of the sixth we pulse in the six-write pulse sequence. data polling must be performed at a sector address within any of the sectors being erased and not at a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the mbm29lv160t/b data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded program algorithm operation and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. see figure 9 for the data polling timing specifications and diagrams. table 9 hardware sequence flags status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded/erase algorithm 0 toggle 0 1 toggle erase suspend mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle (note 1) 00 1 (note 2) exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded/erase algorithm 0 toggle 1 1 n/a erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a 23 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 dq 6 toggle bit i the mbm29lv160t/b also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data can be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six- write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 m s and then stop toggling without the data having changed. in erase, the device will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit i for about 200 m s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. see figure 10 and figure 23 for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions. the oe and we pins will control the output disable functions as described in tables 2 and 3. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 and dq 6 never stops toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit i are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 is high on the second status check, the command may not have been accepted. see table 9: hardware sequence flags. 24 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at dq 2 . dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also table 10 and figure 19. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. notes: 1. performing successive read operations from any address will cause dq 6 to toggle. 2. reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. ry/by ready/busy pin the mbm29lv160t/b provides a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/by pin is low, the devices will not accept any additional program or erase commands with the exception of the erase suspend command. if the mbm29lv160t/b is placed in an erase suspend mode, the ry/by output will be high, by means of connecting with a pull-up resister to v cc . during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. see figure 11 and 12 for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . table 10 toggle bit status mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle erase suspend read (erase suspended sector) (note 1) 11toggle erase-suspend program dq 7 toggle (note 1) 1 (note 2) 25 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 reset hardware reset pin the mbm29lv160t/b device may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least 500 ns in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the device requires an additional t rh before it allows read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. refer to figure 12 for the timing diagram. refer to temporary sector unprotection for additional functionality. if hardware reset occurs during embedded erase algorithm, there is a possibility that the erasing sector(s) will need to be erased again before they can be programmed. word/byte configuration the byte pin selects the byte (8-bit) mode or word (16-bit) mode for the mbm29lv160t/b device. when this pin is driven high, the device operates in the word (16-bit) mode. the data is read and programmed at dq 0 to dq 15 . when this pin is driven low, the device operates in byte (8-bit) mode. under this mode, dq 15 /a -1 pin becomes the lowest address bit and dq 8 to dq 14 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 0 to dq 7 and dq 8 to dq 15 bits are ignored. refer to figures 13 and 14 for the timing diagrams. data protection the mbm29lv160t/b is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine to the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequence. the device also incorporates several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 2.3 v (typically 2.4 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 2.3 v. if the embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) will need to be erased again prior to programming. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not change the command registers. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write, ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to read mode on power-up. handling of son package the metal portion of marking side is connected with internal chip electrically. please pay attention not to occur electrical connection during operation. in worst case, it may be caused permanent damage to device or system by excessive current. 26 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 description a 0 to a 6 dq 0 to dq 15 query-unique ascii string qry 10h 11h 12h 0051h 0052h 0059h primary oem command set 2h: amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min. (write/erase) d7-4: volt, d3-0: 100 mvolt 1bh 0027h v cc max. (write/erase) d7-4: volt, d3-0: 100 mvolt 1ch 0036h v pp min. voltage 1dh 0000h v pp max. voltage 1eh 0000h typical timeout per single b y te/ w ord w r ite 2 n m s 1fh 0004h typical timeout for min. size b uf f er w r ite 2 n m s 20h 0000h typical timeout per individual b l o c k e r ase 2 n m s 21h 000ah typical timeout for full chip e r ase 2 n m s 22h 0000h max. timeout for byte/word write 2 n times typical 23h 0005h max. timeout for buffer write 2 n times typical 24h 0000h max. timeout per individual block erase 2 n times typical 25h 0004h max. timeout for full chip erase 2 n times typical 26h 0000h device size = 2 n byte 27h 0015h flash device interface description 28h 29h 0002h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0004h table 11 common flash memory interface code description a 0 to a 6 dq 0 to dq 15 erase block region 1 information 2dh 2eh 2fh 30h 0000h 0000h 0040h 0000h erase block region 2 information 31h 32h 33h 34h 0001h 0000h 0020h 0000h erase block region 3 information 35h 36h 37h 38h 0000h 0000h 0080h 0000h erase block region 4 information 39h 3ah 3bh 3ch 001eh 0000h 0000h 0001h query-unique ascii string pri 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0030h address sensitive unlock 0 = required 1 = not required 45h 0000h erase suspend 0 = not supported 1 = to read only 2 = to read & write 46h 0002h sector protect 0 = not supported x = number of sectors in per group 47h 0001h sector temporary unprotect 00 = not supported 01 = supported 48h 0001h reserve 49h 4ah 4bh 4ch xxxxh xxxxh xxxxh xxxxh 27 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n absolute maximum ratings storage temperature .................................................................................................. C55c to + 125c ambient temperature with power applied .................................................................. C40c to +85c voltage with respect to ground all pins except a 9 , oe , and reset (note 1) ............ C0.5 v to +v cc +0.5 v v cc (note 1) ................................................................................................................ C0.5 v to +5.5 v a 9 , oe , and reset (note 2) ...................................................................................... C0.5 v to +13.0 v notes: 1. minimum dc voltage on input or l/o pins are C0.5 v. during voltage transitions, inputs may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and l/o pins are v cc +0.5 v. during voltage transitions,outputs may positive overshoot to v cc +2.0 v for periods of up to 20 ns. 2. minimum dc input voltage on a 9 , oe , and reset pins are C0.5 v. during voltage transitions, a 9 , oe , and reset pins may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on a 9 , oe , and reset pins are +13.0 v which may positive overshoot to 14.0 v for periods of up to 20 ns. voltage difference between input voltage and supply voltage (v in C v cc ) do not exceed 9 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating ranges ambient temperature (t a ) mbm29lv160t/b-80 .................................................................................C20c to +70c mbm29lv160t/b-90/-12...........................................................................C40c to +85c v cc supply voltages mbm29lv160t/b-80 .................................................................................+3.0 v to +3.6 v mbm29lv160t/b-90/-12...........................................................................+2.7 v to +3.6 v operating ranges define those limits between which the functionality of the device is quaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. 28 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n maximum overshoot figure 1 maximum negative overshoot waveform +0.6 v C0.5 v 20 ns C2.0 v 20 ns 20 ns figure 2 maximum positive overshoot waveform 1 +2.0 v v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns figure 3 maximum positive overshoot waveform 2 v cc +0.5 v +13.0 v 20 ns +14.0 v 20 ns 20 ns note : this waveform is applied for a 9 , oe , and reset . 29 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n dc characteristics notes: 1. the l cc current listed includes both the dc operating current and the frequency dependent component. 2. l cc active while embedded erase or embedded program is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. (v id C v cc ) do not exceed 9 v. parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max. C1.0 +1.0 a i lo output leakage current v out = v ss to v cc , v cc = v cc max. C1.0 +1.0 a i lit a 9 , oe , reset inputs leakage current v cc = v cc max., a 9 , oe , reset = 12.5 v 35a i cc1 v cc active current (note 1) ce = v il , oe = v ih f = 10 mhz byte 30 ma word 35 ce = v il , oe = v ih f = 5 mhz byte 15 ma word 17 i cc2 v cc active current (note 2) ce = v il , oe = v ih 35ma i cc3 v cc current (standby) v cc = v cc max., ce = v cc 0.3 v, reset = v cc 0.3 v 5a i cc4 v cc current (standby, reset ) v cc = v cc max., reset = v ss 0.3 v 5a i cc5 v cc current (automatic sleep mode) (note 3) v cc = v cc max., ce = v ss 0.3 v, reset = v cc 0.3 v, v in = v cc 0.3 v or v ss 0.3 v 5a v il input low level C0.5 0.6 v v ih input high level 2.0 v cc + 0.3 v v id voltage for autoselect,sector protection, and temporary sector unprotection (a 9 , oe , reset ) (note 4) 11.512.5v v ol output low voltage level i ol = 4.0 ma, v cc = v cc min. 0.45 v v oh1 output high voltage level i oh = C2.0 ma, v cc = v cc min. 2.4 v v oh2 i oh = C100 a v cc C 0.4 v v lko low v cc lock-out voltage 2.3 2.5 v 30 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n ac characteristics ? read only operations characteristics note: test conditions: output load: 1 ttl gate and 30 pf (mbm29lv160t/b-80/-90) 1 ttl gate and 100 pf (mbm29lv160t/b-12) input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbols description test setup -80 (note) -90 (note) -12 (note) unit jedec standard t avav t rc read cycle time min. 80 90 120 ns t avqv t acc address to output delay ce = v il oe = v il max. 80 90 120 ns t elqv t ce chip enable to output delay oe = v il max. 80 90 120 ns t glqv t oe output enable to output delay max. 30 35 50 ns t ehqz t df chip enable to output high-z max. 25 30 30 ns t ghqz t df output enable to output high-z max. 25 30 30 ns t axqx t oh output hold time from address, ce or oe , whichever occurs first min. 0 0 0 ns t ready reset pin low to read mode max. 20 20 20 m s t elfl t elfh ce or byte switching low or high max. 5 5 5 ns figure 4 test conditions c l 3.3 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w notes: c l = 30 pf including jig capacitance (mbm29lv160t/b-80/-90) c l = 100 pf including jig capacitance (mbm29lv160t/b-12) 31 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 ? write (erase/program) operations (continued) parameter symbols description mbm29lv160t/b unit jedec standard -80 -90 -12 t avav t wc write cycle time min. 80 90 120 ns t avwl t as address setup time min. 0 0 0 ns t wlax t ah address hold time min. 45 45 50 ns t dvwh t ds data setup time min. 35 45 50 ns t whdx t dh data hold time min. 0 0 0 ns t oes output enable setup time min. 0 0 0 ns t oeh output enable hold time read min. 0 0 0 ns toggle and data polling min. 10 10 10 ns t ghwl t ghwl read recover time before write min. 0 0 0 ns t ghel t ghel read recover time before write (oe high to ce low) min. 0 0 0 ns t elwl t cs ce setup time min. 0 0 0 ns t wlel t ws we setup time min. 0 0 0 ns t wheh t ch ce hold time min. 0 0 0 ns t ehwh t wh we hold time min. 0 0 0 ns t wlwh t wp write pulse width min. 35 45 50 ns t eleh t cp ce pulse width min. 35 45 50 ns t whwl t wph write pulse width high min. 25 25 30 ns t ehel t cph ce pulse width high min. 25 25 30 ns t whwh1 t whwh1 programming operation byte typ. 88 8 s word 16 16 16 t whwh2 t whwh2 sector erase operation (note 1) typ. 1 1 1 sec t eoe delay time from embedded output enable max. 30 35 50 ns t vcs v cc setup time min. 50 50 50 s t vlht voltage transition time (note 2) min. 4 4 4 s t wpp write pulse width (note 2) min. 100 100 100 s t oesp oe setup time to we active (note 2) min. 4 4 4 s t csp ce setup time to we active (note 2) min. 4 4 4 s t rb recover time from ry/by min. 0 0 0 ns 32 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 (continued) notes: 1. this does not include the preprogramming time. 2. this timing is for sector protection operation. parameter symbols description mbm29lv160t/b unit jedec standard -80 -90 -12 t rh reset hold time before read min. 200 200 200 ns t busy program/erase valid to ry/by delay max. 90 90 90 ns t flqz byte switching low to output high-z max. 30 35 50 ns t fhqv byte switching high to output active min. 30 35 50 ns t vidr rise time to v id (note 2) min. 500 500 500 ns t rp reset pulse width min. 500 500 500 ns 33 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n switching waveforms ? key to switching waveforms figure 5.1 ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h h or l: any change permitted does not apply will be steady will be change from h to l will be change from l to h changing, state unknown center line is high- impedance off state we oe ce t df t ce t oe outputs addresses addresses stable high-z output valid high-z t oeh t acc t rc t oh 34 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 5.2 ac waveforms for hardware reset/read operations reset t acc t oh outputs t rc addresses addresses stable high-z output valid t rh 35 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at word address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.) figure 6 ac waveforms for alternate we controlled program operations t ch t wp t whwh1 t wc t ah ce oe t rc addresses data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df 36 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 7 ac waveforms for alternate ce controlled program operations notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at word address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.) t cp t ds t whwh1 t wc t ah we oe addresses data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd 37 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 8 ac waveforms for chip/sector erase operations * : 1. sa is the sector address for sector erase. addresses = 555h (word), aaaah (byte) for chip erase. 2. these waveforms are for the 16 mode. (the addresses differ from 8 mode.) v cc ce oe addresses data we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h 30h for sector erase 38 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 9 ac waveforms for data polling during embedded algorithm operations *:dq 7 = valid data (the device has completed the embedded operation.) t oeh t oe t whwh1 or 2 ce oe we data t df t ch t ce dq 7 = valid data dq 7 * data dq 0 to dq 6 = output flag (t eoe ) dq0 to dq6 valid data high-z high-z dq 7 dq 0 to dq 6 * figure 10 ac waveforms for taggle bit i during embedded algorithm operations * : dq 6 = stops toggling. (the device has completed the embedded operation.) ce we oe data dq 6 = toggle dq 6 = stop toggling dq 0 to dq 7 data valid t oe dq 6 = toggle t oeh t oes t dh dq 6 39 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 11 ry/by timing diagram during program/erase operations the rising edge of the last we signal ce ry/by we t busy entire programming or erase operations figure 12 reset , ry/by timing diagram t rp reset t ready ry/by we t rb 40 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 13 timing diagram for word mode configuration ce byte oe t elfh t fhqv a -1 dq 0 to dq 7 dq 0 to dq 14 dq 15 dq 15 /a -1 dq 0 to dq 14 figure 14 timing diagram for byte mode configuration ce byte oe dq 15 / a-1 dq 0 to dq 14 t elfl dq 15 dq 0 to dq 14 dq 0 to dq 7 a -1 t flqz 41 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 15 byte timing diagram for write operations ce the falling edge of the last we signal t hold we (t ah ) t set (t as ) input valid byte 42 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 16 ac waveforms for sector protection timing diagram sax = sector address for initial sector say = sector address for next sector note: a -1 is v il on byte mode. t vlht sax say a 0 a 6 a 9 12 v 3 v oe 12 v 3 v t vlht we ce 01h data a 1 a 19 , a 18 , a 17 t vlht a 16 , a 15 , a 14 a 13 , a 12 t wpp t vlht t oesp t csp t oe v cc t vcs 43 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 17 extended sector protection timing diagram spax : sector address to be protected spay : next sector address to be protected time-out : time-out window = 150 m s (min) spax t oe 60h 01h 40h 60h 60h time-out t vcs spax spay t vidr t vlht v cc reset add a 0 a 1 a 6 ce oe we data 44 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 3 v reset v cc ce we ry/by t vlht program or erase command sequence 3 v t vlht t vcs t vidr v id t vlht unprotection period figure 18 temporary sector unprotection timing diagram figure 19 dq 2 vs. dq 6 note: dq 2 is read from the erase-suspended sector. dq 2 dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe 45 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 20 embedded program tm algorithm embedded program tm algorithm * : the sequence is applied for 16 mode. the addresses differ from 8 mode. no yes start program command sequence* (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling device increment address verify byte ? program address/program data programming completed last address ? yes no 46 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 21 embedded erase tm algorithm embedded program tm algorithm * : the sequence is applied for 16 mode. the addresses differ from 8 mode. 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequece (see below) data polling or toggle bit from device erasure completed chip erase command sequence* (address/command): individual sector/multiple sector* erase command sequence (address/command): sector address/30h sector address/30h sector address/30h start data = ffh no yes ? 47 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 22 data polling algorithm * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va =address for programming =any of the sector addresses within the sector being erased during sector erase or multiple erases operation. =any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. fail dq 7 = data? no no dq 7 = data? dq 5 = 1? pass yes yes no start read byte (dq 0 to dq 7 ) addr. = va read byte (dq 0 to dq 7 ) addr. = va yes * 48 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 23 toggle bit algorithm * : dq 6 is rechecked even if dq 5 = 1 because dq 6 may stop toggling at the same time as dq 5 changing to 1. fail dq 6 = toggle ? * yes no dq 6 = toggle dq 5 = 1? pass yes no yes start read byte ? (dq 0 to dq 7 ) addr. = h or l no read (dq 0 to dq 7 ) addr. = h or l 49 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 24 sector protection algorithm * : a -1 is v il on byte mode. setup sector addr. activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes no no plscnt = 1 time out 100 m s read from sector increment plscnt no yes protect another sector? start sector protection data = 01h? plscnt = 25? device failed remove v id from a 9 completed remove v id from a 9 write reset command ( a 1 = v ih , a 0 = v il , oe = v id , a 9 = v id a 6 = ce = v il , reset = v ih ( a 19, a 18 , a 17 , a 16, write reset command addr. = sa, a 6 = v il )* a 0 = v il , a 1 = v ih a 15 , a 14 , a 13 , a 12 ) 50 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 25 temporary sector unprotection algorithm notes: 1. all protected sectors are unprotected. 2. all previously protected sectors are protected once again. reset = v id (note 1) perform erase or program operations reset = v ih start temporary sector unprotection completed (note 2) 51 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 26 embedded programming algorithm for fast mode * : the sequence is applied for 16 mode. * : the addresses differ from 8 mode. yes no 555h/aah verify byte? start fast mode algorithm 555h/20h 2aah/55h xxxxh/a0h program address/program data data polling device last address ? programming completed xxxxh/90h xxxxh/f0h increment address yes no set fast mode in fast program reset fast mode 52 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 figure 27 extended sector protect algorithm to setup sector protect yes no time out 150 m s reset = v id no data = 01h? start extended sector plscnt = 25? read from sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) to sector protect write 60h to sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) wait to 4 m s protect entry? write xxxh/60h plscnt = 1 to verify sector protect write 40h to sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) protect other sector ? no remove v id from reset write reset command increment plscnt remove v id from reset write reset command yes setup next sector address yes device is operating in temporary sector unprotect mode yes fast mode algorithm device failed sector protection completed no 53 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n erase and programming performance n tsop (i) pin capacitance note: test conditions t a = 25c, f = 1.0 mhz n son pin capacitance note: test conditions t a = 25c, f = 1.0 mhz n fbga pin capacitance note: test conditions t a = 25c, f = 1.0 mhz parameter limits unit comments min. typ. max. sector erase time 1 10 sec excludes programming time prior to erasure byte programming time 8 300 s excludes system-level overhead word programming time 16 360 chip programming time 16.8 50 sec excludes system-level overhead erase/program cycle 100,000 cycles parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 7.5 9.5 pf c out output capacitance v out = 0 8 10 pf c in2 control pin capacitance v in = 0 10 13 pf parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 7.5 9.5 pf c out output capacitance v out = 0 8 10 pf c in2 control pin capacitance v in = 0 10 13 pf parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 7.5 9.5 pf c out output capacitance v out = 0 8 10 pf c in2 control pin capacitance v in = 0 10 13 pf 54 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 n package dimensions (continued) 48-pin plastic tsop (i) (fpt-48p-m19) *: resin protruction. (each side: 0.15(.006) max) c 1996 fujitsu limited f48029s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.400.20 (.724.008) 20.000.20 (.787.008) 19.000.20 (.748.008) 0.10(.004) 0.500.10 (.020.004) 0.150.05 (.006.002) 11.50ref (.460) 0.50(.0197) typ 0.200.10 (.008.004) 0.05(0.02)min .043 ?.002 +.004 ?0.05 +0.10 1.10 m 0.10(.004) stand off 1 24 25 48 lead no. * * 12.000.20 (.472.008) height) (mounting dimensions in mm (inches) 55 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 (continued) c 1996 fujitsu limited f48030s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.400.20 (.724.008) 20.000.20 (.787.008) 19.000.20 (.748.008) 0.10(.004) 0.500.10 (.020.004) 0.150.10 (.006.002) 11.50(.460)ref 0.50(.0197) typ 0.200.10 (.008.004) 0.05(0.02)min .043 ?.002 +.004 ?0.05 +0.10 1.10 m 0.10(.004) stand off 1 24 25 48 lead no. * * 12.000.20(.472.008) (mounting dimensions in mm (inches) height) 48-pin plastic tsop (i) (fpt-48p-m20) *: resin protrusion. (each side: 0.15(.006) max) 56 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 (continued) c 1997 fujitsu limited c46002s-4c-3 12.000.10(.472.004) * 46 24 23 1 0.75(.030)max (total height) 0.50(.020)typ m 0.05(.002) index "b" "a" 0.10(.004)typ 0(0)min (stand off) details of "a" part details of "b" part 0.50(.020)typ 0.50(.020)typ 0.320.05 (.013.002) * 10.100.20 10.000.10 (.398.008) (.394.004) 0.05(.002) dimensions in mm (inches) 46-pin plastic son (lcc-46p-m02) note 1) resin residue for * marked dimensions is 0.15 max on a single side. note 2) die pad geometry may change with the models. 57 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 (continued) (continued) c 1998 fujitsu limited c48056s-1c-1 10.00?.10(.394?004) 0.08(.003) 0.40(.016) typ 9.20(.362)ref 1 24 25 48 index index 9.50?.10 (.374?004) 10.00?.20 (.394?008) "a" 0.22?.035 (.009?001) .002 ?0 +.002 ? +0.05 0.05 0.95?.05(.037?002) (mounting height) (stand off) 0.65(.026) 1.15(.045) details of "a" part 0?10 lead no. dimensions in mm (inches) 48-pin plastic csop (lcc-48p-m03) 58 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 (continued) (continued) c 1997 fujitsu limited b48003s-1c-2 9.000.20(.354.008) 0.350.10(.014.004) (stand off) 1.20(.047)max (mounting height) 8.000.20 (.315.008) 0.10(.004) 0.80(.031)nom 5.60(.221) 4.00(.157) ?0.400.10 (.016.004) m ?0.08(.003) 0.80(.031) nom h g fed c b a 6 5 4 3 2 1 index dimensions in mm ( inches ) 48-pin plastic fbga (bga-48p-m03) note: the actual shape of corners may differ from the dimension. 59 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 (continued) c 1998 fujitsu limited b480013s-1c-1 9.00?.20(.354?008) 0.38?.10(.015?004) (stand off) (mounting height) 8.00?.20 (.315?008) 0.10(.004) 0.80(.031)typ 5.60(.221) 4.00(.157) 48- 0.45?.10 (48-.018?004) m 0.08(.003) index hgf edcba 6 5 4 3 2 1 c0.25(.010) .041 ?004 +.006 ?.10 +0.15 1.05 dimensions in mm (inches) 48-pin plastic fbga (bga-48p-m13) note: the actual shape of corners may differ from the dimension. mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f9904 ? fujitsu limited printed in japan |
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